1. Field of the Invention
The present invention is in the field of semiconductor structures. The present invention is further in the field of semiconductor structures of transistor devices. The present invention further relates to the field of integrated devices and circuits. The implementation is not limited to a specific technology, and applies to either the invention as an individual component or to inclusion of the present invention within larger systems which may be combined into larger integrated circuits.
2. Brief Description of Related Art
The semiconductor transistor is the most important component for large integrated circuits. In the last three decades, field effect transistors (FETs) used in current integrated circuit process technologies have undergone a continuous shrinking of the semiconductor area needed for elementary components, and new materials including III-V and II-VI semiconductor compounds have been introduced to improve the device performance. However the need to further improve its general performance while reducing its cost is still a necessity that poses a significant challenge.
In particular, the demand for high bit rate communication, millimeter wave applications and high frequency power conversion requires the development of devices with high cut-off frequencies and low specific RDSon (measured in Ω*mm2). The semiconductor area is directly proportional to the cost of the integrated circuit and a low on-resistance is always desirable to increase the efficiency of the circuit and to reduce the power dissipation and therefore the temperature of the chip. Furthermore, a lower specific on-resistance allows the fabrication of devices with smaller gate capacitance and therefore better RF performance.
One of the main candidates for these applications is the High Electron Mobility Transistors (HEMTs), which generally uses III-V compounds semiconductor materials, such as InAs (indium arsenide), GaAs (gallium arsenide), AlAs (aluminum arsenide) and their alloys (InGaAs and InAlAs) on InP substrate, or III-V Nitride materials such as AN (aluminum nitride), GaN (gallium nitride), InN (indium nitride) and their alloys (AlGaN, InGaN and InAlN). At the present time, very high cut-off frequencies fT have been obtained with these devices.
An example of High electron mobility transistor (HEMT), also known as hetero-structure FET (HFET), is reported in Fujita et al. (U.S. Pat. No. 5,319,223). This device is a field effect transistor incorporating a junction between two materials with different band-gaps (i.e., a hetero-junction) used as channel instead of a doped region as in MOSFET devices. HEMTs avoid impurity scattering through the use of high mobility electrons generated using the hetero junction of a highly-doped wide-band-gap n-type donor-supply layer (e.g. AlGaAs) and a non-doped narrow-band-gap channel layer with no dopant impurities (e.g. GaAs). The electrons generated in the thin n-type wide-band-gap layer drop completely into the narrow-band-gap layer where they are free to move without being affected by impurity scattering. This method to create an electron channel is called modulation doping.
The use of InAs, InAlAs, GaAs and InGaAs materials rather than Si (Silicon) provides two significant advantages. First of all, the room temperature mobility is more than 5 times larger, while the saturation velocity is about twice that of silicon. Second, it is possible to fabricate semi-insulating (SI) GaAs substrates which eliminate the problem of absorbing microwave power in the substrate due to free carrier absorption.
Most of Nitride semiconductors are wide gap semiconductors. For example, GaN and AN exhibit band-gaps of 3.4 eV and 6.2 eV, respectively, at ambient temperature. An advantage of nitride semiconductors is that they have a larger insulation breakdown electric field and a greater electron saturation drift speed than semiconductors such as GaAs or Si. The properties of large band-gap materials (such as GaN) make them ideally suited to operation at elevated temperatures, because they become intrinsic at much higher temperature than narrow band-gap materials, and sustain high current or voltage levels, since they exhibit a high breakdown field.
Furthermore, AlGaN/GaN hetero-structures do not require modulation doping, which is necessary in GaAs-based devices to create the electron gas at the hetero-interface. The discontinuity of the spontaneous polarization, due to the lack of symmetry in wurtzite crystals, induces free carriers at the interface. In addition, the piezoelectric polarization, due to the strain of the AlGaN layer, plays an important role in increasing the density of carriers in the device channel. In general, semiconductor materials with such polarization properties are referred as polar materials. High-power operation has been achieved by GaN based HEMTs in the millimeter wave frequency range.
In FIG. 1 a cross-sectional view of a known hetero-structure field effect transistor is depicted. In this structure, a Channel narrow band-gap layer 3, e.g. GaAs or GaN, and an n-type Barrier layer 5 with a wide band-gap, e.g. AlGaAs or AlGaN, are formed in this order over a substrate 4, e.g. semi-insulating GaAs or sapphire. A source electrode 6 and a drain electrode 2 are formed above the n-type layer 5 with a metal layer deposition. A gate electrode 1 is formed of metallic or semiconductor materials so as to be located between the source electrode 6 and the drain electrode 2. This field-effect transistor is usually a normally ON type FET in which a drain current flows when a OV voltage is applied to the gate, due to the high-concentration two dimensional electron gas generated at the hetero-interface between the n-type AlGaAs (or AlGaN) layer 5 and the un-doped GaAs (or GaN) layer 3.
In order to improve its high-frequency performance, the gate length LG of the device has to be reduced. The Lg reduction allows the minimization of the parasitic capacitances associated with the device. This condition is essential for the improvement of RF performance. However, the reduction of Lg alone does not lead to maximum RF performance. The so-called “short channel effects” involve a shift of the threshold voltage and a deterioration of the transconductance and of the output conductance.
In order to avoid these effects in HEMT devices, the proper layer design must have a high aspect ratio Lg/α where α is the distance between the gate electrode and the two-dimensional electron gas. This scaling down rule involves a limit for HEMT structures due to the gate tunnel current and the degradation of the effective gate length related to the depletion in the recessed regions. In order to increase fT and fmax it is therefore necessary to find alternative solutions so as to improve the actual technology.
Another important limitation of these structures is the difficulty to make them operate in enhancement mode. In case of non-polar or semi-polar materials, such as GaAs (or non polar or semi-polar III-Nitride materials), an enhancement mode device can be obtained removing the n-doping from the barrier layer region underneath the control terminal through the formation of a recessed gate. In FIG. 2 a cross-sectional view of a known enhancement mode hetero-structure field effect transistor employing GaAs and AlGaAs semiconductor materials is depicted. In this structure, delta doping regions 15 and 11 are used to supply carriers to the channel. As it can be seen, the gate has been recessed into the barrier layer 12 in order to remove the modulation doping of the channel under the control terminal 8, and raise the threshold voltage at positive values. A similar result could be obtained also by using two highly doped regions instead of the delta doping profiles.
The enhancement behavior of the previous structure has also another disadvantage: in order to isolate the source and the drain terminals from the gate, the gate region must be made smaller than the etched region formed in the barrier layer, leaving two isolating regions 9 and 7 at the sides of the gate. This causes a discontinuity in the doping modulation of the channel, adding two extra resistive paths in the channel.
HEMT employing polar materials such as GaN and III-Nitride alloys oriented along the [0001] direction, present similar limitations. In these devices, the channel carrier density is a consequence of the polarization discontinuity between the AlGaN (or AN) barrier and the GaN buffer layer, and cannot be removed by simply recessing the gate. A solution to this problem has been proposed in Ueno et al. (U.S. Pat. No. 7,528,423) where an insulating layer has been inserted between the metal gate electrode and the barrier layer, so that an improvement in the device transconductance and a reduction in the gate leakage current can be achieved.
The solution proposed by Ueno et al. however, requires a very thin barrier layer with very low Al concentrations in order to achieve positive threshold voltage values. This is due to the lack of stable metal alloys with high work-function to be used as gate electrode. This solution therefore degrades the carrier confinement in the GaN channel layer and is very susceptible to process variations. Furthermore the maximum threshold voltage achievable is of the order of few mV.
Another interesting solution for this problem is illustrated in FIG. 3 and was proposed by Kaibara et al. (U.S. Pat. No. 7,663,161). More in particular, as a potential structure for realizing the normally-off type FET, a HFET structure was proposed in which a p-type GaN layer 17, formed on the top of a barrier layer of un-doped AlGaN 21, was used as a gate for the device. The proposed device included also a channel layer of un-doped GaN 19 under the AlGaN barrier 21, where the electron channel is formed.
In this structure, the piezoelectric polarization, generated at the hetero-interface between the GaN channel layer 19 and the AlGaN barrier layer 21, is offset by the piezoelectric polarization generated at the hetero-interface between the AlGaN barrier layer and the GaN control layer 17. As a result, the concentration of two-dimensional electron gas (2DEG) below the GaN control layer is selectively reduced. The use of a p-doped gate further lowers the Fermi energy into the channel thereby achieving the normally-off characteristic.
The solution proposed by Ueno et al., even if very efficient in order to obtain an enhancement mode GaN device, still does not solve the problem associated with the parasitic gate diode that can turn on at moderate low positive gate voltages limiting the electron enhancement in the channel portion under the gate. If the gate voltage is brought to high enough voltage values, an injection of low mobility holes in the channel allows an increase of the electron population. However, if holes are injected into the channel, their recombination time limits the switching speed of the device deteriorating the overall device performance.
Furthermore, in general p-type dopant in compound semiconductor are not easy to deal with respect to n-type ones. For example, in III-N semiconductors the p-doping process is complicated by the following effects: large thermal activation energy of 120-200 meV which requires high annealing temperatures, hydrogen passivation of MOCVD-grown GaN-acceptor bounds, and significant acceptor reactor memory leading to broad dopant profiles.
There is therefore a need for a new device structure which can operate in normally-off conditions, without presenting strong limitations on the gate bias, with a threshold voltage easily tunable at the desired value and, at the same time, a reduced gate leakage current.
Although the cited prior art references describe structures that offer some of the described advantages, no one device includes all of them, limiting their ability to solve the problem of obtaining transistors with high RF performance, low power dissipation and low on-resistance per given semiconductor area in integrated circuits.
It is therefore a purpose of the present invention to describe a novel structure of a semiconductor transistor that offers the advantage of improved performances in terms of on-resistance and power consumption combined with a drastically reduction of the gate leakage current and a easily tunable threshold voltage.